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bcm2835.hpp
1 /*
2  Title --- driver/bcm2835.hpp
3 
4  Copyright (C) 2013 Giacomo Trudu - wicker25[at]gmail[dot]com
5 
6  This file is part of Rpi-hw.
7 
8  Rpi-hw is free software: you can redistribute it and/or modify
9  it under the terms of the GNU Lesser General Public License as published by
10  the Free Software Foundation version 3 of the License.
11 
12  Rpi-hw is distributed in the hope that it will be useful,
13  but WITHOUT ANY WARRANTY; without even the implied warranty of
14  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  GNU Lesser General Public License for more details.
16 
17  You should have received a copy of the GNU Lesser General Public License
18  along with Rpi-hw. If not, see <http://www.gnu.org/licenses/>.
19 */
20 
21 
22 #ifndef _RPI_HW_IFACE_BCM2835_HPP_
23 #define _RPI_HW_IFACE_BCM2835_HPP_
24 
25 #include <unistd.h>
26 #include <fcntl.h>
27 #include <sys/mman.h>
28 
29 #include <rpi-hw/rpi.hpp>
30 
31 #include <rpi-hw/consts.hpp>
32 #include <rpi-hw/types.hpp>
33 #include <rpi-hw/exception.hpp>
34 #include <rpi-hw/utils.hpp>
35 
36 #define BCM2708_PERI_BASE 0x20000000
37 
38 #define CLOCK_BASE (BCM2708_PERI_BASE + 0x00101000)
39 #define GPIO_BASE (BCM2708_PERI_BASE + 0x00200000)
40 #define GPIO_PWM (BCM2708_PERI_BASE + 0x0020C000)
41 
42 #define NUM_OF_PINS 54
43 #define PAGE_SIZE (4*1024)
44 #define BLOCK_SIZE (4*1024)
45 
46 namespace rpihw { // Begin main namespace
47 
48 /*!
49  @namespace rpihw::driver
50  @brief Namespace of the main driver.
51 */
52 
53 namespace driver { // Begin drivers namespace
54 
55 /*!
56  @class bcm2835
57  @brief Broadcom BCM2835 controller.
58 */
59 class bcm2835 {
60 
61 public:
62 
63  //! BCM2708 registers.
64  enum Registers {
65 
66  /* ================== GPIO Controller registers ================== */
67 
68  /*!
69  @section title GPIO Function Select Registers (0 to 5)
70 
71  The function select registers are used to define the operation of the general-purpose I/O pins.
72  Each of the 54 GPIO pins uses 3 bit to select the function, therefore all registers contain
73  at most 10 GPIO.
74 
75  @code
76  ====================GPFSEL====================
77  pin - 9 8 7 6 5 4 3 2 1 0
78  0. xx 000 000 000 000 000 000 000 000 000 000 32 bit = 3 x 10 pin + 2 reserved
79  pin - 19 18 17 16 15 14 13 12 11 10
80  1. xx 000 000 000 000 000 000 000 000 000 000 ...
81  pin - 29 28 27 26 25 24 23 22 21 20
82  2. xx 000 000 000 000 000 000 000 000 000 000 ...
83  pin - 39 38 37 36 35 34 33 32 31 30
84  3. xx 000 000 000 000 000 000 000 000 000 000 ...
85  pin - 49 48 47 46 45 44 43 42 41 40
86  4. xx 000 000 000 000 000 000 000 000 000 000 ...
87  pin - - - - - - - 53 52 51 50
88  5. xx xxx xxx xxx xxx xxx xxx 000 000 000 000 32 bit = 3 x 4 pin + 20 reserved
89  ==============================================
90  @endcode
91 
92  @section code Codes
93 
94  @li 000 = GPIO pin X is an input
95  @li 001 = GPIO pin X is an output
96  @li 100 = GPIO pin X takes alternate function 0
97  @li 101 = GPIO pin X takes alternate function 1
98  @li 110 = GPIO pin X takes alternate function 2
99  @li 111 = GPIO pin X takes alternate function 3
100  @li 011 = GPIO pin X takes alternate function 4
101  @li 010 = GPIO pin X takes alternate function 5
102  */
103 
104  GPFSEL0 = 0, // 0x 7E20 0000
105  GPFSEL1 = 1, // 0x 7E20 0004
106  GPFSEL2 = 2, // 0x 7E20 0008
107  GPFSEL3 = 3, // 0x 7E20 000C
108  GPFSEL4 = 4, // 0x 7E20 0010
109  GPFSEL5 = 5, // 0x 7E20 0014
110 
111  /*!
112  @section title GPIO Pin Output Set Registers (0 to 1)
113 
114  @code
115  =================GPSET===============
116  pin 31 ... ... 0
117  0. 00000000000000000000000000000000 32 bit = 32 pin
118  pin 53 ... ... 32
119  1. xxxxxxxx000000000000000000000000 32 bit = 24 pin + 8 reserved
120  =====================================
121  @endcode
122 
123  @section Codes
124 
125  @li 0 = No effect
126  @li 1 = Set GPIO pin X
127  */
128 
129  GPSET0 = 7, // 0x 7E20 001C
130  GPSET1 = 8, // 0x 7E20 0020
131 
132  /*!
133  @section title GPIO Pin Output Clear Registers (0 to 1)
134 
135  @code
136  =================GPCLR===============
137  pin 31 ... ... 0
138  0. 00000000000000000000000000000000 32 bit = 32 pin
139  pin 53 ... ... 32
140  1. xxxxxxxx000000000000000000000000 32 bit = 24 pin + 8 reserved
141  =====================================
142  @endcode
143 
144  @section code Codes
145 
146  @li 0 = No effect
147  @li 1 = Clear GPIO pin n
148  */
149 
150  GPCLR0 = 10, // 0x 7E20 0028
151  GPCLR1 = 11, // 0x 7E20 002C
152 
153  /*!
154  @section title GPIO Pin Level Registers (0 to 1)
155 
156  @code
157  =================GPLEV===============
158  pin 31 ... ... 0
159  0. 00000000000000000000000000000000 32 bit = 32 pin
160  pin 53 ... ... 32
161  1. xxxxxxxx000000000000000000000000 32 bit = 24 pin + 8 reserved
162  =====================================
163  @endcode
164 
165  @section code Codes
166 
167  @li 0 = GPIO pin X is low
168  @li 1 = GPIO pin X is high
169  */
170 
171  GPLEV0 = 13, // 0x 7E20 0034
172  GPLEV1 = 14, // 0x 7E20 0038
173 
174  /*!
175  @section title GPIO Event Detect Status Registers (0 to 1)
176 
177  @code
178  =================GPEDS===============
179  pin 31 ... ... 0
180  0. 00000000000000000000000000000000 32 bit = 32 pin
181  pin 53 ... ... 32
182  1. xxxxxxxx000000000000000000000000 32 bit = 24 pin + 8 reserved
183  =====================================
184  @endcode
185 
186  @section code Codes
187 
188  @li 0 = Event not detected on GPIO pin X
189  @li 1 = Event detected on GPIO pin X
190  */
191 
192  GPEDS0 = 15, // 0x 7E20 0040
193  GPEDS1 = 16, // 0x 7E20 0044
194 
195  /*!
196  @section title GPIO Rising Edge Detect Enable Registers (0 to 1)
197 
198  @code
199  =================GPREN===============
200  pin 31 ... ... 0
201  0. 00000000000000000000000000000000 32 bit = 32 pin
202  pin 53 ... ... 32
203  1. xxxxxxxx000000000000000000000000 32 bit = 24 pin + 8 reserved
204  =====================================
205  @endcode
206 
207  @section code Codes
208 
209  @li 0 = Rising edge detect disabled on GPIO pin X
210  @li 1 = Rising edge on GPIO pin X sets corresponding bit in GPEDS
211  */
212 
213  GPREN0 = 18, // 0x 7E20 004C
214  GPREN1 = 19, // 0x 7E20 0050
215 
216  /*!
217  @section title GPIO Falling Edge Detect Enable Registers (0 to 1)
218 
219  @code
220  =================GPFEN===============
221  pin 31 ... ... 0
222  0. 00000000000000000000000000000000 32 bit = 32 pin
223  pin 53 ... ... 32
224  1. xxxxxxxx000000000000000000000000 32 bit = 24 pin + 8 reserved
225  =====================================
226  @endcode
227 
228  @section code Codes
229 
230  @li 0 = Falling edge detect disabled on GPIO pin X
231  @li 1 = Falling edge on GPIO pin X sets corresponding bit in GPEDS
232  */
233 
234  GPFEN0 = 21, // 0x 7E20 0058
235  GPFEN1 = 22, // 0x 7E20 005C
236 
237  /*!
238  @section title GPIO High Detect Enable Registers (0 to 1)
239 
240  @code
241  =================GPHEN===============
242  pin 31 ... ... 0
243  0. 00000000000000000000000000000000 32 bit = 32 pin
244  pin 53 ... ... 32
245  1. xxxxxxxx000000000000000000000000 32 bit = 24 pin + 8 reserved
246  =====================================
247  @endcode
248 
249  @section code Codes
250 
251  @li 0 = High detect disabled on GPIO pin X
252  @li 1 = High on GPIO pin n sets corresponding bit in GPEDS
253  */
254 
255  GPHEN0 = 24, // 0x 7E20 0064
256  GPHEN1 = 25, // 0x 7E20 0068
257 
258  /*!
259  @section title GPIO Low Detect Enable Registers (0 to 1)
260 
261  @code
262  =================GPLEN===============
263  pin 31 ... ... 0
264  0. 00000000000000000000000000000000 32 bit = 32 pin
265  pin 53 ... ... 32
266  1. xxxxxxxx000000000000000000000000 32 bit = 24 pin + 8 reserved
267  =====================================
268  @endcode
269 
270  @section code Codes
271 
272  @li 0 = Low detect disabled on GPIO pin X
273  @li 1 = Low on GPIO pin n sets corresponding bit in GPEDS
274  */
275 
276  GPLEN0 = 27, // 0x 7E20 0070
277  GPLEN1 = 28, // 0x 7E20 0074
278 
279  /*!
280  @section title GPIO Pull-up/down Register
281 
282  @code
283  =================GPPUD===============
284  0. xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00 32 bit = 2 control bits + 8 reserved
285  =====================================
286  @endcode
287 
288  @section code Codes
289 
290  @li 00 = Disable pull-up/down
291  @li 01 = Enable pull-down control
292  @li 10 = Enable pull-up control
293  @li 11 = Reserved
294  */
295 
296  GPPUD0 = 37, // 0x 7E20 0094
297 
298  /*!
299  @section title GPIO Pull-up/down Clock Registers (0 to 1)
300 
301  The GPIO Pull-up/down Clock Registers control the actuation of internal pull-downs on
302  the respective GPIO pins.
303  These registers must be used in conjunction with the GPPUD register to effect
304  GPIO Pull-up/down changes. The following sequence of events is required:
305 
306  -# Write to GPPUD to set the required control signal
307  -# Wait 150 cycles – this provides the required set-up time for the control signal
308  -# Write to GPPUDCLK0/1 to clock the control signal into the GPIO pads you wish to modify
309  -# Wait 150 cycles – this provides the required hold time for the control signal
310  -# Write to GPPUD to remove the control signal
311  -# Write to GPPUDCLK0/1 to remove the clock
312 
313  @code
314  ===============GPPUDCLK==============
315  pin 31 ... ... 0
316  0. 00000000000000000000000000000000 32 bit = 32 pin
317  pin 53 ... ... 32
318  1. xxxxxxxx000000000000000000000000 32 bit = 24 pin + 8 reserved
319  =====================================
320  @endcode
321 
322  @section code Codes
323 
324  @li 0 = No effect
325  @li 1 = Assert clock on line X
326  */
327 
328  GPPUDCLK0 = 38, // 0x 7E20 0098
329  GPPUDCLK1 = 39, // 0x 7E20 009C
330 
331 
332  /** ================== PWM Controller registers ================== **/
333 
334  /*!
335  @section title PWM Control
336 
337  @code
338  ==================CTL================
339  xxxxxxxxxxxxxxxxx0x0000000000000 32 bit = 14 fields + 18 reserved
340  =====================================
341  @endcode
342 
343  @section title CTL Register
344 
345  @code
346  Bit Field name Description
347  =================================================================
348  15 MSEN2 Channel 2 M/S enable
349  0 = PWM algorithm is used
350  1 = M/S transmission is used
351  -----------------------------------------------------------------
352  13 USEF2 Channel 2 use FIFO
353  0 = Data register is transmitted
354  1 = Fifo is used for transmission
355  -----------------------------------------------------------------
356  12 POLA2 Channel 2 polarity
357  0 = 0->low 1->high
358  1 = 0->high 1->low
359  -----------------------------------------------------------------
360  11 SBIT2 Channel 2 silence bit
361  Defines the state of the output
362  when no transmission takes place.
363  -----------------------------------------------------------------
364  10 RPTL2 Channel 2 repeat last data
365  0 = Transmission interrupts when
366  FIFO is empty
367  1 = Last data in FIFO is
368  transmitted repetedly until
369  FIFO is not empty
370  -----------------------------------------------------------------
371  9 MODE2 Channel 2 mode
372  0 = PWM mode
373  1 = Serialiser mode
374  -----------------------------------------------------------------
375  8 PWEN2 Channel 2 enable
376  0 = Channel is disabled
377  1 = Channel is enabled
378  -----------------------------------------------------------------
379  7 MSEN1 Channel 1 M/S enable
380  0 = PWM algorithm is used
381  1 = M/S transmission is used
382  -----------------------------------------------------------------
383  6 CLRF1 Clear FIFO
384  0 = Clears FIFO
385  1 = Has no effect
386  This is a single shot operation.
387  This bit always reads 0.
388  -----------------------------------------------------------------
389  5 USEF1 Channel 1 use FIFO
390  0 = Data register is transmitted
391  1 = Fifo is used for transmission
392  -----------------------------------------------------------------
393  4 POLA1 Channel 1 use FIFO
394  0 = 0->low 1->high
395  1 = 0->high 1->low
396  -----------------------------------------------------------------
397  3 SBIT1 Channel 1 silence bit
398  Defines the state of the output
399  when no transmission takes place.
400  -----------------------------------------------------------------
401  2 RPTL1 Channel 1 repeat last data
402  0 = Transmission interrupts when
403  FIFO is empty
404  1 = Last data in FIFO is
405  transmitted repetedly until
406  FIFO is not empty
407  -----------------------------------------------------------------
408  1 MODE1 Channel 1 mode
409  0 = PWM mode
410  1 = Serialiser mode
411  -----------------------------------------------------------------
412  0 PWEN1 Channel 1 enable
413  0 = Channel is disabled
414  1 = Channel is enabled
415  =================================================================
416  @endcode
417  */
418 
419  PWM_CTL = 1, // 0x 7E20 C000
420 
421  /*!
422  @section title PWM Status
423 
424  @code
425  ==================STA================
426  xxxxxxxxxxxxxxxxxxxx000000000000 32 bit = 12 fields + 20 reserved
427  =====================================
428  @endcode
429 
430  @section title STA Register
431 
432  @code
433  Bit Field name Description
434  =============================================================
435  12 STA4 Channel 4 state
436  11 STA3 Channel 3 state
437  10 STA2 Channel 2 state
438  9 STA1 Channel 1 state
439  8 BERR Bus error flag
440  7 GAPO4 Channel 4 gap cccurred flag
441  6 GAPO3 Channel 3 gap cccurred flag
442  5 GAPO2 Channel 2 gap cccurred flag
443  4 GAPO1 Channel 1 gap cccurred flag
444  3 RERR1 FIFO read error flag
445  2 WERR1 FIFO write error flag
446  1 EMPT1 FIFO empty flag
447  0 FULL1 FIFO full flag
448  =============================================================
449  @endcode
450  */
451 
452  PWM_STA = 2, // 0x 7E20 C004
453 
454  /*!
455  @section title DMAC Register
456 
457  @code
458  =================DMAC================
459  0xxxxxxxxxxxxxxxx000000000000000 32 bit = 16 fields + 16 reserved
460  =====================================
461  @endcode
462 
463  @section title DMAC Register
464 
465  @code
466  Bit Field name Description
467  =============================================================
468  31 ENAB DMA Enable
469  15:8 PANIC DMA Threshold for PANIC signal
470  7:0 DREQ DMA Threshold for DREQ signal
471  =============================================================
472  @endcode
473  */
474 
475  PWM_DMAC = 3, // 0x 7E20 C008
476 
477  /*!
478  @section title PWM Channel 1 Range
479 
480  @code
481  =================RNG1================
482  0. 00000000000000000000000000000000 32 bit = 32 fields
483  =====================================
484  @endcode
485  */
486 
487  PWM_RNG1 = 4, // 0x 7E20 C010
488 
489  /*!
490  @section title PWM Channel 1 Data
491 
492  @code
493  =================DAT1================
494  0. 00000000000000000000000000000000 32 bit = 32 fields
495  =====================================
496  @endcode
497  */
498 
499  PWM_DAT1 = 5, // 0x 7E20 C014
500 
501  /*!
502  @section title PWM FIFO Input
503 
504  @code
505  =================FIF1================
506  0. 00000000000000000000000000000000 32 bit = 32 fields
507  =====================================
508  @endcode
509  */
510 
511  PWM_FIF1 = 6, // 0x 7E20 C018
512 
513  /*!
514  @section title PWM Channel 2 Range
515 
516  @code
517  =================RNG2================
518  0. 00000000000000000000000000000000 32 bit = 32 fields
519  =====================================
520  @endcode
521  */
522 
523  PWM_RNG2 = 7, // 0x 7E20 C020
524 
525  /*!
526  @section title PWM Channel 2 Data
527 
528  @code
529  =================DAT2================
530  0. 00000000000000000000000000000000 32 bit = 32 fields
531  =====================================
532  @endcode
533  */
534 
535  PWM_DAT2 = 8 // 0x 7E20 C024
536  };
537 
538 
539  //! Raspberry Pi pins.
540  enum RpiPins {
541 
542  #if RPI_REVISION == 0x0002 || RPI_REVISION == 0x0003
543 
544  PIN3 = 0, PIN5 = 1, PIN7 = 4,
545  PIN8 = 14, PIN10 = 15, PIN11 = 17,
546  PIN12 = 18, PIN13 = 21, PIN15 = 22,
547  PIN16 = 23, PIN18 = 24, PIN19 = 10,
548  PIN21 = 9, PIN22 = 25, PIN23 = 11,
549  PIN24 = 8, PIN26 = 7
550 
551  #else
552 
553  PIN3 = 2, PIN5 = 3, PIN7 = 4,
554  PIN8 = 14, PIN10 = 15, PIN11 = 17,
555  PIN12 = 18, PIN13 = 27, PIN15 = 22,
556  PIN16 = 23, PIN18 = 24, PIN19 = 10,
557  PIN21 = 9, PIN22 = 25, PIN23 = 11,
558  PIN24 = 8, PIN26 = 7
559 
560  #endif
561 
562  };
563 
564  //! Constructor method.
565  bcm2835();
566 
567  //! Destructor method.
568  virtual ~bcm2835();
569 
570  /*!
571  @brief Sets the mode of a GPIO pin.
572  @param[in] pin The GPIO pin.
573  @param[in] mode The GPIO mode.
574  @param[in] pull_mode The pull resistor mode.
575  */
576  void setup( uint8_t pin, uint8_t mode, uint8_t pull_mode = PULL_OFF );
577 
578  /*!
579  @brief Sets the value of a output pin.
580  @param[in] pin The output pin.
581  @param[in] value The value of output pin.
582  */
583  void write( uint8_t pin, bool value );
584 
585  /*!
586  @brief Returns the value of a input pin.
587  @param[in] pin The input pin.
588  @return The value of input pin.
589  */
590  bool read( uint8_t pin ) const;
591 
592  /*!
593  @brief Returns the event state of a GPIO pin.
594  @param[in] pin The GPIO pin.
595  @return The event state.
596  */
597  bool checkEvent( uint8_t pin ) const;
598 
599  /*!
600  @brief Enables/disables the rising edge event on a GPIO pin.
601  @param[in] pin The GPIO pin.
602  @param[in] enabled If \c true enable the rising edge event.
603  */
604  void setRisingEvent( uint8_t pin, bool enabled );
605 
606  /*!
607  @brief Enables/disables the falling edge event on a GPIO pin.
608  @param[in] pin The GPIO pin.
609  @param[in] enabled If \c true enable the falling edge event.
610  */
611  void setFallingEvent( uint8_t pin, bool enabled );
612 
613  /*!
614  @brief Enables/disables the high event on a GPIO pin.
615  @param[in] pin The GPIO pin.
616  @param[in] enabled If \c true enable the high event.
617  */
618  void setHighEvent( uint8_t pin, bool enabled );
619 
620  /*!
621  @brief Enables/disables the low event on a GPIO pin.
622  @param[in] pin The GPIO pin.
623  @param[in] enabled If \c true enable the low event.
624  */
625  void setLowEvent( uint8_t pin, bool enabled );
626 
627  /*!
628  @brief Enables/disables the pull-up/down control on a GPIO pin.
629  @param[in] pin The GPIO pin.
630  @param[in] mode The pull resistor mode.
631  */
632  void setPullUpDown( uint8_t pin, uint8_t mode );
633 
634 private:
635 
636  //! File descriptor of `/dev/mem`.
637  int m_mem_fd;
638 
639  //! GPIO controller virtual address.
640  volatile uint32_t *m_gpio;
641 
642  //! PWM controller virtual address.
643  volatile uint32_t *m_pwm;
644 
645  /*!
646  @brief Sets a bit value on one of the GPIO controller registers.
647  @param[in] offset The register offset.
648  @param[in] index The bit position.
649  @param[in] value The bit value.
650  */
651  void setBit( uint8_t offset, uint8_t index, bool value );
652 
653  /*!
654  @brief Returns a bit value from one of the GPIO controller registers.
655  @param[in] offset The register offset.
656  @param[in] index The bit position.
657  @return The bit value.
658  */
659  bool getBit( uint8_t offset, uint8_t index ) const;
660 
661  /*!
662  @brief Wait some CPU cycles.
663  @param[in] cycles Number of CPU cycles.
664  */
665  void waitCycles( size_t cycles ) const;
666 };
667 
668 } // End of drivers namespace
669 
670 } // End of main namespace
671 
672 
673 // Include inline methods
674 #include <rpi-hw/driver/bcm2835-inl.hpp>
675 
676 #endif /* _RPI_HW_IFACE_BCM2835_HPP_ */
bool checkEvent(uint8_t pin) const
Returns the event state of a GPIO pin.
Definition: bcm2835-inl.hpp:69
void setLowEvent(uint8_t pin, bool enabled)
Enables/disables the low event on a GPIO pin.
Registers
BCM2708 registers.
Definition: bcm2835.hpp:64
void setPullUpDown(uint8_t pin, uint8_t mode)
Enables/disables the pull-up/down control on a GPIO pin.
int m_mem_fd
File descriptor of /dev/mem.
Definition: bcm2835.hpp:637
void setup(uint8_t pin, uint8_t mode, uint8_t pull_mode=PULL_OFF)
Sets the mode of a GPIO pin.
virtual ~bcm2835()
Destructor method.
void setFallingEvent(uint8_t pin, bool enabled)
Enables/disables the falling edge event on a GPIO pin.
Definition: bcm2835-inl.hpp:87
volatile uint32_t * m_gpio
GPIO controller virtual address.
Definition: bcm2835.hpp:640
volatile uint32_t * m_pwm
PWM controller virtual address.
Definition: bcm2835.hpp:643
void setBit(uint8_t offset, uint8_t index, bool value)
Sets a bit value on one of the GPIO controller registers.
Definition: bcm2835-inl.hpp:30
bcm2835()
Constructor method.
bool getBit(uint8_t offset, uint8_t index) const
Returns a bit value from one of the GPIO controller registers.
Definition: bcm2835-inl.hpp:37
void setHighEvent(uint8_t pin, bool enabled)
Enables/disables the high event on a GPIO pin.
Definition: bcm2835-inl.hpp:96
void write(uint8_t pin, bool value)
Sets the value of a output pin.
Definition: bcm2835-inl.hpp:51
void setRisingEvent(uint8_t pin, bool enabled)
Enables/disables the rising edge event on a GPIO pin.
Definition: bcm2835-inl.hpp:78
Broadcom BCM2835 controller.
Definition: bcm2835.hpp:59
void waitCycles(size_t cycles) const
Wait some CPU cycles.
Definition: bcm2835-inl.hpp:44
bool read(uint8_t pin) const
Returns the value of a input pin.
Definition: bcm2835-inl.hpp:60
RpiPins
Raspberry Pi pins.
Definition: bcm2835.hpp:540